1. Field of the Invention
The present invention relates to a semiconductor device having an element isolation structure in the main surface of a semiconductor substrate and a method of manufacturing the same, and more particularly, it relates to a semiconductor device whose element isolation structure is an STI structure having a bird's beak on its upper end and a method of manufacturing the same.
2. Description of the Background Art
In a semiconductor device structured as an integrated circuit, a number of semiconductor elements are formed in active regions of a semiconductor substrate. An element isolation structure electrically isolates these semiconductor elements from each other, for preventing unnecessary interference thereamong. At the same time, in order to implement prescribed functions for which the integrated circuit is designed, an electrical conductor (wire) formed on the element isolation structure selectively connects these semiconductor elements with each other.
When element isolation is incomplete, a leakage current flows between the semiconductor elements. When still another semiconductor element recognizes the leakage current as a signal, it follows that the integrated circuit malfunctions. Therefore, element isolation must be completely performed in order to keep operations of the integrated circuit normal, and hence it can be said that element isolation is an important technique.
In a semiconductor device of such a generation that the minimum line width on a silicon substrate is set to not more than 0.2 .mu.m, its element isolation structure changes from a conventional LOCOS (local oxidation of silicon) structure to an STI (shallow trench isolation) structure. The conventional element isolation structure formed by a LOCOS method has such disadvantages that (1) a large bird's beak remarkably corrodes and narrows active regions, (2) a channel stop impurity layer formed in a substrate region located under the LOCOS structure is re-distributed in a later heat treatment step, (3) the thickness of a LOCOS oxide film changes between a narrow pitch (width of the element isolation structure or the active regions) and a wide pitch, and (4) a lithography process becomes difficult due to large steps between the active regions and the element isolation structure.
Element isolation by the STI structure has been proposed as a method of solving these problems. Steps of forming the same are briefly described. First, a trench of about 0.1 to 0.5 .mu.m in depth is formed on the main surface of a silicon substrate by anisotropic etching, and thereafter filled with an insulator. This insulator is flattened by CMP (chemical mechanical polishing) or the like, thereby completing an STI element isolation structure. Since such flattening is performed, the step between the main surface of the semiconductor substrate and the surface of the element isolation structure is smaller as compared with that in an element isolation structure formed by the LOCOS method.
The STI element isolation structure is formed in an initial stage among a series of steps for forming an integrated circuit. In other words, the STI element isolation structure is formed in a step before source and drain regions of a MOS (metal oxide semiconductor) transistor are formed by ion implantation in the vicinity of surfaces of active regions holding the element isolation structure. The STI element isolation structure suppresses such a disadvantage that a channel of a parasitic MOSFET (MOS field-effect transistor) is formed in a field region (region of the element isolation structure: element isolation region) between the active regions. Consequently, an integrated circuit having a small leakage current between active regions holding an element isolation structure is implemented regardless of presence/absence of operations of a MOSFET.
The STI structure is an element isolation structure essentially free from a bird's beak, i.e., involving no bird's beak. In the STI structure free from a bird's beak, however, stress resulting from the shape of a trench forming the STI structure concentrates to a corner part (part between the bottom and the side wall) on the bottom of the trench or the upper end (i.e., opening end) of the trench, to result in formation of a defect in a silicon substrate. When a defect is formed around the trench, a leakage current is increased when the MOSFET is turned off, to remarkably increase power consumption of the semiconductor device.
It is known as a conventional technique that the inner wall of the trench is oxidized thereby the shape of the corner part on the bottom of the trench is rounded while simultaneously a small bird's beak is formed on the upper end of the trench thereby the shape of the trench is rounded so that the stress is relaxed. In this technique, however, it follows that a small bird's beak is formed from the element isolation structure toward the active regions despite the STI structure.
A series of steps of forming an STI structure including a step of forming a bird's beak are now described in detail. FIGS. 48 to 58 are step diagrams showing a conventional method of forming an STI structure. In order to form the STI structure, a silicon dioxide film 102, a polysilicon film 103 and a silicon nitride film 104 are formed in this order on a silicon substrate 101, as shown in FIG. 48. The silicon dioxide film 102 is also referred to as an underlayer oxide film.
The step shown in FIG. 49 is then carried out. In the step shown in FIG. 49, resist is applied onto the silicon nitride film 104 and thereafter patterned through a transfer step, for forming a resist mask 105. Thereafter the resist mask 105 is employed as a mask (screen) for executing anisotropic etching, thereby selectively removing the silicon nitride film 104. Since the ratio of the etching rates for the silicon nitride film 104 and the polysilicon film 103 is sufficiently large, the anisotropic etching stops on the upper surface of the polysilicon film 103. In this step, the resist mask 105 is also partially removed by the etching. If the quantity of this overetching is large, the resist mask 105 may be entirely removed.
In the subsequent step shown in FIG. 50, the resist mask 105 is removed and thereafter anisotropic etching is executed through the patterned silicon nitride film 104 employed as a hard mask, thereby selectively removing the polysilicon film 103, the silicon dioxide film 102 and the silicon substrate 101 in this order. Needless to say, etchants employed for the anisotropic etching are properly changed following stepwise change of the films to be removed in this step. Through this step, a trench 106 of about 300 nm in depth, for example, is formed in the silicon substrate 101. In the anisotropic etching performed on the silicon substrate 101, the etching rate for polysilicon is larger than that for single-crystalline silicon. Therefore, the inner wall of the polysilicon film 103 slightly retreats through the step shown in FIG. 50.
Then, as shown in FIG. 51, an inner wall silicon dioxide film 107 of about 50 nm in thickness is formed on the inner wall of the trench 106 by thermal oxidation. This treatment is referred to as inner wall oxidation. The inner wall oxidation is performed in order to round the shape of a corner part on the bottom of the trench 106 or that of the upper end of the trench 106 for attaining an effect of relaxing stress, as described above. In addition to this effect, an effect of introducing an etching damage layer formed on the surface part of the inner wall of the trench 106 by the anisotropic etching into the inner wall silicon dioxide film 107 for reducing defects (point defects, dislocations etc.) in the silicon substrate 101 and an effect of reducing interface state density between the STI structure and the silicon substrate 101 are also attained by performing the inner wall oxidation.
In the step shown in FIG. 51, the inner wall of the polysilicon film 103 and part of the silicon substrate 101 coming into contact with the silicon dioxide film 102 are simultaneously oxidized to form a bird's beak 108 on the upper end of the trench 106. A thermal oxide film of polysilicon grows at a higher rate than that of single-crystalline silicon, and hence the thickness of a silicon dioxide film formed on the polysilicon film 103 is larger than that of a silicon dioxide film formed on the silicon substrate 101. Consequently, the bird's beak length (the thickness of the bird's beak 108 along the main surface of the silicon substrate 101) is larger than the thickness of the remaining part of the inner wall silicon dioxide film 107. Needless to say, active regions are reduced as the thickness of the inner wall silicon dioxide film 107 is increased. When the active regions are reduced, the gate width of a MOS transistor is reduced, for example, and hence a drain current disadvantageously falls below a designed value.
It is possible to assume a method of omitting the step of depositing the polysilicon film 103 and directly depositing the silicon nitride film 104 on the silicon dioxide film 102 in order to reduce the bird's beak length. In this case, however, stress caused on the upper end of the trench 108 is disadvantageously increased as compared with the case of providing the polysilicon film 103, depending on the conditions.
Then, the trench 106 covered with the inner wall silicon dioxide film 107 is filled with silicon dioxide 109, for example, as shown in FIG. 52. This step is carried out by depositing the silicon dioxide 109 to cover the upper surface of the silicon nitride film 104, the side surfaces of the silicon nitride film 104 and the polysilicon film 103, the side surface of the underlayer dioxide film 102 and the inner wall of the silicon substrate 101 by a film formation method such as HDP (high density plasma)-CVD (chemical vapor deposition), for example, simultaneously performing etching and film formation. The trench 107 may be basically filled with any insulation such as silicon dioxide, silicon oxynitride or TEOS, for example.
Then, CMP (chemical mechanical polishing) is performed through the silicon nitride film 104 serving as a stopper thereby flattening the upper end of the silicon dioxide 109, as shown in FIG. 53. After this flattening step, the silicon dioxide 109 remains in the trench 106.
Then, the silicon nitride film 104 and the polysilicon film 103 are removed by etching, as shown in FIG. 54.
Then, as FIG. 55 shows, the upper portion of the silicon dioxide 109 is removed by etching, for leaving silicon dioxide 120 as a principal component of the STI structure. At this time, part of the bird's beak 108 and the silicon dioxide film 102 are simultaneously removed by etching. If the inner wall silicon dioxide film 107 is thick and hence the bird's beak 108 is also thick, the upper end of the STI structure is not depressed toward the silicon substrate 101, as shown by symbol F in FIG. 55. If the bird's beak 108 is thin or the etching is overetching, however, a depressed part 110 is caused as shown by symbol G in FIG. 56.
Then, the following step is carried out for forming a structure shown in FIG. 57 or 58 for the structure of FIG. 55 or FIG. 56. In this step, an underlayer oxide film is first formed in a thickness of 10 nm to 20 nm to cover the main surface of the silicon substrate 101 and heat-treated at a temperature of 800.degree. C. to 1100.degree. C. This treatment, performed for densifying the silicon dioxide 120 filled into the trench 106, is referred to as thermal shrinking. After the thermal shrinking step, well implantation (ion implantation for forming a well in the silicon substrate 101), channel stopper implantation (ion implantation for forming a channel stopper in the silicon substrate 101) and channel implantation (ion implantation for forming a channel in the silicon substrate 101) are performed and thereafter the aforementioned underlayer oxide film is removed by etching. Then, the main surface of the silicon substrate 101 is thermally oxidized thereby forming a gate insulator film 111, and then a gate electrode 112 is deposited. Consequently, the structure shown in FIG. 57 or 58 is completed.
When the depressed part 110 is formed as shown in FIG. 58, the gate electrode 112 is formed to partially fill up the depressed part 110. Therefore, even if the thickness of the gate insulator film 111 and a voltage applied to the gate electrode 112 are uniform between a plurality of semiconductor elements, electric field strength on the upper end of the STI structure is greater in the region G shown in FIG. 58 having the depressed part 110 as compared with the region F shown in FIG. 57 having no depressed part 110. This results from the difference in the thickness (bird's beak length) of the bird's beak 108. In the structure shown in FIG. 58 having the depressed part 110, therefore, a potential is bent larger in the vicinity of the upper end of the STI structure in the silicon substrate 101, to reduce the threshold voltage in this region. In the vicinity of the center of the active region separate from the upper end of the STI structure, on the other hand, the threshold voltage remains substantially identical between the structures shown in FIGS. 57 and 58 due to the same structure.
The ratio of an end of the STI structure to the gate width (width of the active regions) is increased when the gate width is reduced, and hence, as shown in a graph of FIG. 59, the threshold voltage is reduced in the structure shown in FIG. 58 having the depressed part 110 (curve C11). While the threshold voltage is reduced when the gate width is reduced also in the structure shown in FIG. 57 having no depressed part 110 (curve C10), the degree of this reduction is small.
The threshold voltage is reduced also in the structure shown in FIG. 57 since the amount of a channel dopant introduced into the silicon substrate 101 is reduced as compared with the center of the active region when channel implantation is performed through the thick bird's beak 108 with low energy. Although the threshold voltage must be increased when the bird's beak 108 is thick since an effective gate insulator film thickness on the upper end of the STI structure is increased as compared with the centers of the active region, an effect of reducing the amount (dose) of ions introduced into the silicon substrate 101 is large if the energy for channel implantation is low and hence the threshold voltage tends to slightly lower as the gate width is reduced as a whole. If the channel implantation is performed with high energy and therefore the ions are implanted into the silicon substrate 101 by about 100% through the thick bird's beak 108 in the channel implantation, the threshold voltage tends to increase as the gate width is reduced. The effect of thus increasing the threshold voltage as the gate width is reduced is referred to as "narrow channel effect" and an effect of reducing the threshold voltage as the gate width is reduced is referred to as "inverse narrow channel effect".
Therefore, it is disadvantageous that the inverse narrow channel effect becomes remarkable when the depressed part 110 is present on the upper end of the STI structure, as shown in FIG. 59. This is because the threshold voltage is remarkably dispersed as the inverse narrow channel effect becomes remarkable when the finished gate width fluctuates, to cause a malfunction of the semiconductor device or reduction of the yield.
FIG. 60 is a graph showing a gate voltage-to-drain current characteristic of a MOSFET employing the aforementioned STI structure for element isolation. As shown on a curve C13, a hump HP appears when the depressed part 110 is present on the upper end of the STI structure. This is because the potential is bent more largely on the gate end as compared with the center of the active region to reduce the threshold voltage on the gate end due to concentration of an electric field in the vicinity of the depressed part 110 in the silicon substrate 101 and hence a drain current flows as a leakage current at a gate voltage lower than the threshold voltage at the center of the active region. This characteristic is also a sign of the inverse narrow channel effect. Thus, the drain current flows in a standby state of the MOSFET when the inverse narrow channel effect results from the depressed part 110, to disadvantageously increase power consumption of the semiconductor device.
While it is effective to increase the thickness of the bird's beak 108 in order to prevent formation of the depressed part 110 on the end of the STI structure, the area of the active region is disadvantageously reduced in this case. When the width of the active regions is reduced, the effective gate width is also reduced to disadvantageously reduce the drain current of the MOSFET.
The trench 106 is formed by anisotropically etching the silicon substrate 101, and hence dangling bonds (unsaturated bonds of silicon atoms) or irregular grain structures are formed in the vicinity of the side wall and the bottom surface of the trench 106 in the silicon substrate 101. After formation of the STI structure, source/drain regions (a set of source and drain regions formed in one MOSFET are generically referred to as "source/drain regions") are formed on the active regions of the silicon substrate 101 by ion implantation, and thereafter high-temperature heat treatment is performed. Thus, ions implanted into the active regions are electrically activated and crystal defects present in the silicon substrate 101 disappear to recover the crystallographic order of the silicon substrate 101. In this high-temperature heat treatment, an impurity such as boron having a relatively high impurity diffusion coefficient diffuses to reach the STI structure. When irregular grain structures are present, the impurity acceleratingly diffuses along the grain boundaries thereof to reach the STI structure. Further, the dangling bonds provide proper bond sites for the diffusing impurity species, and hence it follows that the impurity is accumulated on the interface of the STI structure or in the vicinity thereof.
It is known that, when impurity species are present in an STI structure, defects follow in relatively high density. In relation to this, the following phenomena are observed: (1) Dislocations are formed in the vicinity of the STI structure in the silicon substrate 101 due to clusters of the impurity species. (2) A voltage necessary for dielectric breakdown of the STI structure is reduced as the defect density (or the dopant concentration) in the STI structure is increased. Consequently, dielectric breakdown takes place on a portion of the STI structure having high defect density (dopant concentration) when a voltage is applied to the source/drain regions formed adjacently to the STI structure. Further, a leakage current resulting from defects flows in or around the STI structure, and hence the threshold voltage is reduced in the vicinity of the side wall of the STI structure.
The chip area of the semiconductor device must be reduced in order to save the cost for manufacturing the same, and hence the isolation width of the STI structure tends to reduce. Therefore, the parasitic capacitance between active regions must be reduced in order to guarantee element isolability among semiconductor elements formed on the active regions. This parasitic capacitance depends on the element isolation width and the relative dielectric constant of the insulator filled into the STI structure. More specifically, the parasitic capacitance between two active regions isolated by the STI structure is proportional to the dielectric constant of the insulator filled into the STI structure and substantially inverse proportional to the element isolation width. The relative dielectric constant is that of a substance normalized with a vacuum dielectric constant. SiO.sub.2 is known as a representative insulator filled into the STI structure. The relative dielectric constant of SiO.sub.2, which is about 3.7 to 3.9 is by no means small. When the element isolation width is reduced, therefore, the parasitic capacitance is problematically increased. Following this, an isolation breakdown voltage is also reduced. Further, a leakage current flows between source/drain regions of one MOSFET and those of another MOSFET, to result in a malfunction of the integrated circuit.